In this module we will study automatic test pattern generation (ATPG) using sensitization–propagation -justification approach. We will first introduce the basics of. 1. VLSI Design Verification and Testing. Combinational ATPG Basics. Mohammad Tehranipoor. Electrical and Computer Engineering. University of Connecticut. Boolean level. • Classical ATPG algorithms reach their limits. ➢ There is a need for more efficient ATPG tools! 6. Circuits. • Basic gates. – AND, OR, EXOR, NOT.

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It is also called a permanent fault model because the faulty effect is assumed to be permanent, in contrast to intermittent faults which occur seemingly at random and transient faults which occur sporadically, perhaps depending on operating conditions e.

This allows using a relatively simple atpt matrix to quickly test all the comprising FFs, as well as to trace failures to specific FFs.

Combinational ATPG Basics

ATPG efficiency is another important consideration that is influenced by the fault model under consideration, the type of circuit under test full scansynchronous sequential, or asynchronous sequentialthe level of attpg used to represent the circuit under test gate, register-transfer, switchand the required test quality.

The combinational ATPG method allows testing the individual nodes or flip-flops of the logic circuit without being concerned with the operation of the overall circuit. A fault model is a mathematical description of how a baskcs alters design behavior.

Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. Fault propagation moves the resulting signal xtpg, or fault effect, forward by sensitizing a path from the fault site to a primary output. Testing very-large-scale integrated circuits with a high fault coverage is a difficult task because of complexity.


In the past several decades, the most popular fault model used in practice is the single stuck-at fault model. Second, it is possible that a detection pattern exists, but the algorithm cannot find one. This model is used to describe faults for CMOS logic gates. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. A fault is said to be detected by a test pattern if the output of that test pattern, when testing a device that has only that one fault, is different than the expected output.

Bridging to VDD or Vss is equivalent to stuck at fault model. Removing equivalent faults from entire set of faults is called fault collapsing. The effectiveness of ATPG is measured by the number of modeled defects, or fault modelsdetectable and by the number of generated patterns.

Automatic test pattern generation

However, these test generators, combined with low-overhead DFT techniques such as partial scanhave shown a certain degree of success in testing large designs. For designs that are sensitive to area or performance overhead, the solution of using sequential-circuit ATPG and partial scan offers an attractive alternative to the popular full-scan solution, which is based on combinational-circuit ATPG.

In stuck-short, a transistor behaves as it is always conducts or stuck-onand stuck-open is when a transistor never conducts current or stuck-off. Any single fault from the set of equivalent faults can represent the whole set. Sequential-circuit ATPG searches for a sequence of test vectors to detect a particular fault through the space of all possible test vector sequences.

However, according to reported results, no single strategy or heuristic out-performs others for all applications or circuits. The single stuck-at fault model is structural because it is defined based on a structural gate-level circuit model.


NPTEL :: Computer Science and Engineering – VLSI Design Verification and Test

In the latter case, dominant driver keeps its value, while the other one baics the AND or OR value of its own and the dominant driver. By using this site, you agree to the Terms of Use and Privacy Policy. These metrics generally indicate test quality higher with more fault detections and test application time higher with more patterns.

The output of a test pattern, when testing a fault-free device that works exactly as designed, is called the expected output of that test pattern. First, the fault may be intrinsically undetectable, such that no patterns exist that can detect that particular fault. From Wikipedia, the free encyclopedia. ATPG is a topic that is covered by several conferences attpg the year. Equivalent faults produce the same faulty behavior for all input patterns.

Therefore, many different ATPG methods have been developed to address atph and sequential circuits. This page was last edited on 23 Novemberat The generated patterns are used to test semiconductor devices after manufacture, or to assist with determining the cause of failure failure analysis [1]. Retrieved from ” https: Views Read Edit View history. Hence, if a circuit has n signal lines, there are potentially 2n stuck-at faults defined on the circuit, bwsics which some can be viewed as being equivalent to others.